Method and system for a differential switched capacitor array for a voltage controlled oscillator (VCO) or a local oscillator (LO) buffer

ABSTRACT

Methods and systems for increasing an amplifier circuit&#39;s Q factor are disclosed herein. The method may comprise coupling a first LC tank to a source of a single switching transistor and coupling a second LC tank to a drain of the single switching transistor. A gate of the single switching transistor may be controlled by an amplifier core coupled to the first LC tank and the second LC tank. A resistance of the first LC tank and the second LC tank may be decreased by about one half, which increases the Q factor by about two. The gate of the single switching transistor may be controlled by a control signal generator coupled to the amplifier core. The first LC tank and/or the second LC tank may be tuned to a frequency of about 3.4 GHz to 4 GHz. The single switching transistor may comprise an NMOS transistor.

RELATED APPLICATIONS

This application is related to the following applications, each of whichis incorporated herein by reference in its entirety for all purposes:

-   -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16149US01) filed ______, 2004;    -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16150US01) filed ______, 2004;    -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16151US01) filed ______, 2004;    -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16152US01) filed ______, 2004;    -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16153US01) filed ______, 2004;    -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16154US01) filed ______, 2004;    -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16155US01) filed ______, 2004;    -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16157US01) filed ______, 2004;    -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16158US01) filed ______, 2004;    -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16162US01) filed ______, 2004;    -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16228US01) filed ______, 2004;    -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16229US01) filed ______, 2004;    -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16230US01) filed ______, 2004;    -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16234US01) filed ______, 2004;    -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16236US01) filed ______, 2004; and    -   U.S. patent application Ser. No. ______ (Attorney Docket No.        16237US01) filed ______, 2004.

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[Not Applicable]

MICROFICHE/COPYRIGHT REFERENCE

[Not Applicable]

FIELD OF THE INVENTION

Certain embodiments of the invention relate to the processing of radiosignals in a receiver and/or transceiver. More specifically, certainembodiments of the invention relate to a method and system for adifferential switched capacitor array for a voltage controlledoscillator (VCO) or a local oscillator (LO) buffer.

BACKGROUND OF THE INVENTION

Modern communication devices, such as radio frequency (RF) communicationdevices, process electromagnetic wave signals with variable signalstrength. The signal strength varies depending on distance between atransmitter and a receiver, as well as environmental factors andprocess, temperature etc. variations (PVT). A power amplifier (PA) isutilized prior to signal transmission by a transmitter, for example, anda variable gain low noise amplifier (LNA) is utilized after a signal isreceived by a receiver, to amplify the signal and adjust the signal gainaccordingly.

Conventional amplifying devices, such as LNAs, PAs, and/or buffers, aswell as voltage controlled oscillators (VCOs) and other differentialinput/output circuits, utilize one or more circuits with switchedcapacitor tuning. One or more switched capacitors may utilize separateswitches that turn ON and/or OFF individual capacitors to achievecircuit and signal tuning. Conventional switched capacitors, however,are characterized by an inherent resistance factor generated by eachswitch. Such inherent resistance is directly proportional to the qualityfactor of the circuit and/or device utilizing the switched capacitortuning. As a result, the device quality factor, as well as the deviceefficiency, deteriorate With the use of switched capacitor tuning.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of ordinary skill in the artthrough comparison of such systems with the present invention as setforth in the remainder of the present application with reference to thedrawings.

BRIEF SUMMARY OF THE INVENTION

Certain embodiments of the invention may be found in a method and systemfor increasing a Q factor of an amplifier circuit. The method maycomprise coupling a first LC tank to a source of a single switchingtransistor and coupling a second LC tank to a drain of the singleswitching transistor. A gate of the single switching transistor may becontrolled by an amplifier core coupled to the first LC tank and thesecond LC tank. The amplifier core coupled to the first LC tank and thesecond LC tank may control a gate of the single switching transistor todecrease resistance by about one half, which increases the Q factor byabout two. The gate of the single switching transistor may be controlledby a control signal generator coupled to the amplifier core. The firstLC tank and/or the second LC tank may be tuned to a frequency of about3.4 GHz to 4 GHz.

The single switching transistor may comprise an NMOS transistor. A firstplurality of LC tanks may be coupled to the first LC tank. The firstplurality of LC tanks may comprise LC tanks connected in parallel and/ora binary weighted array of switchable capacitors. A second plurality ofLC tanks may be coupled to the second LC tank. The second plurality ofLC tanks may comprise LC tanks connected in parallel and/or a binaryweighted array of switchable capacitors. The source of the singleswitching transistor may be coupled to a second switching transistor andthe drain of the single switching transistor may be coupled to a thirdswitching transistor.

The system may comprise a first LC tank that is coupled to a source of asingle switching transistor and a second LC tank that is coupled to adrain of the single switching transistor. An amplifier core may becoupled to the first LC tank and the second LC tank. The amplifier coremay control a gate of the single switching transistor decrease aresistance of the first LC tank and the second LC tank by about onehalf, thus increasing the Q factor by about two. A control signalgenerator may be coupled to the amplifier core, and the control signalgenerator may be adapted to control the gate of the single switchingtransistor. The amplifier core may tune the first LC tank and/or thesecond LC tank to a frequency of about 3.4 GHz to 4 GHz.

The single switching transistor may comprise an NMOS transistor. A firstplurality of LC tanks may be coupled to the first LC tank, where thefirst plurality of LC tanks may comprise LC tanks connected in paralleland/or as a binary weighted array of switchable capacitors. A secondplurality of LC tanks may be coupled to the second LC tank, where thesecond plurality of LC tanks may comprise LC tanks connected in paralleland/or as a binary weighted array of switchable capacitors. A secondswitching transistor may be coupled to the source of the singleswitching transistor and a third switching transistor may be coupled tothe drain of the single switching transistor.

These and other features and advantages of the present invention may beappreciated from a review of the following detailed description of thepresent invention, along with the accompanying figures in which likereference numerals refer to like parts throughout.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a circuit illustrating an amplifier circuit that may beutilized in connection with an embodiment of the invention.

FIG. 2 is a circuit illustrating a binary weighted capacitor array thatmay be utilized in connection with an embodiment of the invention.

FIG. 3 is a circuit illustrating an amplifier circuit with LC tuningtanks and switchable transistors that may be utilized in connection withan embodiment of the invention.

FIG. 4 is a circuit illustrating an amplifier circuit with differentialswitched capacitor array, in accordance with an embodiment of theinvention.

FIG. 5 is a circuit illustrating a differential switched capacitor arraywith DC biasing transistors that may be utilized in connection with anembodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Certain aspects of the invention may be found in a method and system forincreasing an amplifier circuit's Q factor. An amplifying device, suchas a low noise amplifier (LNA), a power amplifier (PA), and/or a buffer,as well as an oscillator, such as a voltage controlled oscillator (VCO),may utilize one or more signal tuning circuits comprising one or moreswitched capacitors. For example, a VCO and/or an amplifying device mayutilize an inductance-capacitance (LC) tank for tuning one or moresignals, where a switch, such as an NMOS transistor, may be utilized toselectively turn ON and/or OFF the tuning LC tank.

In an exemplary embodiment of the invention, a VCO may be utilizedwithin a radio frequency (RF) transceiver and one or more LC tanks maybe utilized within the VCO to tune a differential output of the VCO. TheVCO, and the corresponding differential output LC-tanks, may be adaptedfor tuning over a broad range of frequencies, such as from about 3.4 GHzto about 4 GHz, for example. Resistance associated with each switchwithin the switched capacitor LC-tuning tanks may be reduced byconnecting corresponding differential switched capacitors in series,separated by a single switching transistor, rather than two separatetransistors for each differential LC-tank. In this manner, by reducingthe number of switching transistors and the corresponding resistanceassociated with the switch, the quality factor of the circuit, Q, may beproportionately increased.

FIG. 1 is a circuit illustrating an amplifier circuit 100 that may beutilized in connection with an embodiment of the invention. Referring toFIG. 1, the amplifier circuit 100 may comprise an amplifier core 102,inductors 112 and 114, capacitors 108 and 110, and a voltage supply rail116. In operation, the LC-tank comprising inductor 112 and capacitor 108and/or the LC-tank comprising inductor 114 and capacitor 110 may betuned to a resonance frequency f₀. For example, the LC-tank comprisinginductor 112 and capacitor 108 and/or the LC-tank comprising inductor114 and capacitor 110 may be tuned to a frequency range of about 3.4 GHzto about 4 GHz. The amplifier core 102 may comprise suitable circuitryor logic and may be adapted to amplify an incoming differential signaland generate an output differential signal.

The amplifier circuit 100 may be utilized for signal amplificationimmediately after a signal is received by a receiver, for example. Inaddition, the amplifier circuit 100 may also be utilized to amplify asignal prior to transmission. Depending on the particular application,the amplifier core 102 may be utilized with additional circuitry, suchas a mixer, to downconvert or upconvert a signal, if the amplifiercircuit 100 is used in a receiver LNA or a transmitter PA, respectively.

In one aspect of the invention, the amplifier circuit 100 may beimplemented in buffers and/or VCOs that utilize switched capacitortuning. In this manner, the differential output LC-tank comprisinginductor 112 and capacitor 108 and/or the LC-tank comprising inductor114 and capacitor 110 may be adapted to utilize one or more switchesthat turn capacitor 108 and/or capacitor 110 ON or OFF. The capacitorswitches may comprise one or more NMOS transistors, for example. Theamplifying circuit 100, and the corresponding differential outputLC-tank comprising inductor 112 and capacitor 108 and/or the LC-tankcomprising inductor 114 and capacitor 110, may be adapted for tuningover a broad range of frequencies, such as from about 3.4 GHz to about 4GHz, for example.

The tuning frequency f₀ of each differential output LC-tank may bedetermined from the following equation:$f_{0} = \frac{1}{2\Pi\sqrt{LC}}$Since the tuning frequency f₀ depends on the capacitance of the LC-tank,one or more LC-tanks may be utilized in parallel for each differentialoutput of the amplifying circuit 100. In addition, each LC-tank mayutilize switched capacitors for improved tuning capabilities of theamplifying circuit 100.

FIG. 2 is a circuit illustrating a binary weighted capacitor array 200that may be utilized in connection with an embodiment of the invention.Referring to FIG. 2, the binary weighted capacitor array 200 may beimplemented in an electric signal processing device, such as a VCOand/or a local oscillator (LO) buffer, for example, that may utilizedifferential switched capacitor tuning over a broad range offrequencies. For example, a VCO may utilize the binary weightedcapacitor array 200 in a GSM radio during generation of a differentialoscillator signal at frequency range of about 3.4 GHz to about 4 GHz.

The binary weighted capacitor array 200 may comprise a 7-bit switchedcapacitor array and may be a part of one or more LC-tanks within a VCO,for example. In this regard, the binary weighted capacitor array 200 maycomprise switched capacitors C0 through C7 with correspondingtransistors M0 through M7. Each of the legs in the 7-bit switchedcapacitor array may comprise a switched capacitor and a switchingtransistor and each leg is coupled in parallel. The last leg, however,does not comprise a switching transistor but only comprises a capacitor.

In one aspect of the invention, each of the switched capacitors Cnwithin the 7-bit binary weighted capacitor array 200 may be selectedwith capacitance that is a 2^(n) multiple of a capacitance unit “C.”Single capacitor C8 may be selected with capacitance at (128*C), forexample. Capacitor C0 may be selected with capacitance (2⁰*C), whichequals C. Similarly, capacitor M6 may be selected with capacitance(2⁶*C), which equals (64*C). The seventh capacitor C7 may then beselected with capacitance (128*C). In this manner, the total capacitanceof capacitors C0 through C7 may equal (255*C), which is approximatelytwice as large as the capacitance C8.

Switching transistors M0 through M7 may comprise NMOS transistors, forexample, and may be adapted to selectively switch each correspondingcapacitor ON or OFF. By utilizing switched capacitor tuning, the binaryweighted capacitor array 200 may be adapted to selectively change thetotal capacitance of the LC-tank and achieve a broad tuning frequencyrange. However, since each switching transistor may be characterized byan inherent resistance factor, the quality factor Q of the LC-tank andthe VCO may be decreased with the number of switches utilized in thebinary weighted capacitor array 200.

The quality factor Q of the LC-tank with a switching transistor may bedetermined from the following equation:${Q = \frac{1}{{C\left( {2\Pi\quad f_{0}} \right)}R}},$where C is the capacitance of the LC-tank and R is the switchingtransistor equivalent ON resistance. Since the quality factor Q of thecircuit is inversely proportional to the equivalent ON resistance R ofthe switching transistor, the quality factor Q of the LC-tank and theVCO may be decreased with the number of switches utilized in the binaryweighted capacitor array 200.

In one aspect of the invention, the quality factor Q of the LC-tank andthe VCO may be improved by a factor of about two by connecting eachdifferential pair of corresponding switched capacitors in series,separated by a single switching transistor, instead of two separateswitches for each differential switched capacitor. By utilizing a singleswitching transistor, the resulting resistance within the differentialLC-tank may be reduced by a factor of about two, thereby increasing thequality factor Q of the circuit by a factor of about two.

FIG. 3 is a circuit illustrating an amplifier circuit 300 with LC tuningtanks and switchable transistors that may be utilized in connection withan embodiment of the invention. Referring to FIG. 3, the amplifiercircuit 300 may comprise an amplifier core 302, a voltage supply rail304 for supply voltage V_(DD), inductors L1 and L2, capacitors C1through C_(n) corresponding to inductor L1, and capacitors C′1 throughC′_(n), corresponding to inductor L2. Inductor L1 and capacitors C1through C_(n) may form a first LC-tank and inductor L2 and capacitorsC′1 through C′_(n) may form a second LC-tank. The first and secondLC-tank within the amplifying circuit 300 may be adapted to tune theamplifying circuit and generate a differential output signal that maycover a broad frequency range.

In operation, the first or second LC-tank may be tuned to a resonancefrequency f₀. For example, the first and second LC-tank within theamplifying circuit 300 may be tuned to resonate at about 3.4 GHz toabout 4 GHz, for an incoming differential signal, such as a multibandsignal. The amplifier core 302 may comprise suitable circuitry or logicand may be adapted to amplify the incoming differential signal togenerate an output differential signal.

In one aspect of the invention, the amplifier circuit 300 may beimplemented in a local oscillator (LO) buffer and/or a voltagecontrolled oscillator (VCO), for example, that utilize differentialswitched capacitor tuning. In this manner, the first and seconddifferential output LC-tanks comprising inductors L1 and L2 andcapacitors C1 through C_(n) and C′1 through C′_(n) may be adapted toutilize one or more switches that turn capacitors C1 through C_(n) andC′1 through C′_(n) ON or OFF. Accordingly, each of the capacitors C1through C_(n) and C′1 through C′_(n) may utilize switching transistorsM1 through M_(n) and M′1 through M′_(n), respectively. The capacitorswitches M1 through M_(n) and M′1 through M′_(n) may comprise one ormore NMOS transistors, for example.

In another aspect of the invention, the quality factor Q of the firstand second LC-tank within the amplifying circuit 300 may be improved bya factor of about two by connecting each differential pair ofcorresponding switched capacitors in series, separated by a singleswitching transistor, instead of two separate switches for eachdifferential switched capacitor. By utilizing a single switchingtransistor, the resulting resistance within the differential LC-tank maybe reduced by a factor of about two, thereby increasing the qualityfactor Q of the circuit by a factor of about two. For example, capacitorC1 may be connected in series with corresponding capacitor C′1,separated by only one switching transistor. Additional differentialswitched capacitor pairs may also be coupled in this manner, therebyresulting in an increase in the quality factor Q of the amplifyingcircuit 300.

FIG. 4 is a circuit illustrating an amplifier circuit 400 with adifferential switched capacitor array, in accordance with an embodimentof the invention. Referring to FIG. 4, the amplifier circuit 400 maycomprise an amplifier core 402, a voltage supply rail 404 for supplyvoltage V_(DD), inductors L1 and L2, capacitors C1 and C2, switchingtransistor M0 and a control signal (CS) generator 403. Inductor L1 andcapacitor C1 may form a first LC-tank and inductor L2 and capacitor C2may form a second LC-tank. The first and second LC-tank within theamplifying circuit 400 may be adapted to tune the amplifying circuit andgenerate a differential output signal that may cover a broad frequencyrange.

In operation, the first or second LC-tank may be tuned to a resonancefrequency f₀. For example, the first and second LC-tank within theamplifying circuit 400 may be tuned to resonate at about 3.4 GHz toabout 4 GHz, for an incoming differential signal, such as a multibandsignal. The amplifier core 302 may comprise suitable circuitry or logicand may be adapted to amplify the incoming differential signal togenerate an output differential signal.

In another aspect of the invention, the quality factor Q of the firstand second LC-tank within the amplifying circuit 400 may be improved bya factor of about two by connecting the differential pair ofcorresponding switched capacitors C1 and C2 in series, separated by thesingle switching transistor M0. The first and second LC tank parameters,such as capacitance, inductance, switching transistor size, and switchequivalent ON resistance may stay the same as prior to connecting thetwo capacitors C1 and C2 in series. However, only one of the twoswitching transistors may be utilized resulting in a decrease in theswitch effective ON resistance by about two. Since the quality factor Qis inversely proportionate to the switch equivalent ON resistance R,reducing R by about two may result in increasing the quality factor Q byabout two.

A source of the NMOS switching transistor M0 may be coupled to capacitorC2 and a drain of the switching transistor M0 may be coupled tocapacitor C1. The gate of switching transistor M0 may be adapted toreceive a control signal (CS). The control signal may be generated bythe amplifier core 402 and/or by the CS generator 403. If a controlsignal is generated by the amplifier core 402 and/or the CS generator403 and communicated to the switch M0, the switch M0 may turndifferential switched capacitors C1 and C2 ON. If the amplifier core 402and/or the CS generator 403 stop generation of the control signal, theswitch M0 may be turned OFF, which may result in the capacitors C1 andC2 being turned OFF, or resulting in the capacitors C1 and C2 berepresented as floating capacitors.

Referring again to FIG. 4, there is also illustrated equivalencycircuits for instances when the switching transistor M0 is turned ON.The inherent resistance of the switching transistor M0 may berepresented as R. By utilizing the single switching transistor M0, theresulting resistance R within the differential LC-tank may be reduced bya factor of about two, thereby increasing the quality factor Q of thecircuit by a factor of about two. This may be represented as individualresistors with resistance R/2 being coupled to each of the differentialswitched capacitors C1 and C2.

FIG. 5 is a circuit illustrating a differential switched capacitor array500 with DC biasing transistors that may be utilized in connection withan embodiment of the invention. Referring to FIG. 5, the differentialswitched capacitor array 500 may be the differential switched capacitorarray C1-M0-C2 illustrated on FIG. 4. In one aspect of the invention,the differential switched capacitor array 500 may also utilize switchingtransistors M1 and M2. Switching transistors M1 and M2 may comprise NMOStransistors and may be utilized within the differential switchedcapacitor array 500 to establish a DC path, or a 0V voltage between thecapacitors C1 and C2 when the switching transistor M0 is OFF andcapacitors C1 and C2 may be represented as floating capacitors.

Even though the present invention may be implemented with regard toswitched capacitor tuning in an amplifying device, such as an LNA, a PA,and/or a buffer, a local oscillator buffer or within a VCO, theinvention may not be so limited. A differential switched capacitor arraywith capacitors connected in series and separated by a switch may beimplemented in any electronic signal processing device that may utilizedifferential switched capacitor tuning.

Accordingly, aspects of the invention may be realized in hardware,software, firmware or a combination thereof. The invention may berealized in a centralized fashion in at least one computer system, or ina distributed fashion where different elements are spread across severalinterconnected computer systems. Any kind of computer system or otherapparatus adapted for carrying out the methods described herein issuited. A typical combination of hardware, software and firmware may bea general-purpose computer system with a computer program that, whenbeing loaded and executed, controls the computer system such that itcarries out the methods described herein.

One embodiment of the present invention may be implemented as a boardlevel product, as a single chip, application specific integrated circuit(ASIC), or with varying levels integrated on a single chip with otherportions of the system as separate components. The degree of integrationof the system will primarily be determined by speed and costconsiderations. Because of the sophisticated nature of modernprocessors, it is possible to utilize a commercially availableprocessor, which may be implemented external to an ASIC implementationof the present system. Alternatively, if the processor is available asan ASIC core or logic block, then the commercially available processormay be implemented as part of an ASIC device with various functionsimplemented as firmware.

The invention may also be embedded in a computer program product, whichcomprises all the features enabling the implementation of the methodsdescribed herein, and which when loaded in a computer system is able tocarry out these methods. Computer program in the present context maymean, for example, any expression, in any language, code or notation, ofa set of instructions intended to cause a system having an informationprocessing capability to perform a particular function either directlyor after either or both of the following: a) conversion to anotherlanguage, code or notation; b) reproduction in a different materialform. However, other meanings of computer program within theunderstanding of those skilled in the art are also contemplated by thepresent invention.

While the invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the present invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the present invention without departing from its scope.Therefore, it is intended that the present invention not be limited tothe particular embodiments disclosed, but that the present inventionwill include all embodiments falling within the scope of the appendedclaims.

1. A method for increasing an amplifier circuit's Q factor, the methodcomprising: coupling a first LC tank to a source of a single switchingtransistor; coupling a second LC tank to a drain of said singleswitching transistor; and controlling a gate of said single switchingtransistor by an amplifier core coupled to said first LC tank and saidsecond LC tank to cause a resistance of said first LC tank and saidsecond LC tank to decrease by about one half, thereby increasing the Qfactor by about two.
 2. The method according to claim 1, furthercomprising controlling said gate of said single switching transistor bya control signal generator coupled to said amplifier core.
 3. The methodaccording to claim 1, further comprising tuning at least one of saidfirst LC tank and second LC tank to a frequency of about 3.4 GHz to 4GHz.
 4. The method according to claim 1, wherein said single switchingtransistor comprises an NMOS transistor.
 5. The method according toclaim 1, further comprising coupling a first plurality of LC tanks tosaid first LC tank.
 6. The method according to claim 5, wherein saidfirst plurality of LC tanks comprises LC tanks connected in parallel. 7.The method according to claim 5, wherein said first plurality of LCtanks comprises a binary weighted array of switchable capacitors.
 8. Themethod according to claim 1, further comprising coupling a secondplurality of LC tanks to said second LC tank.
 9. The method according toclaim 8, wherein said second plurality of LC tanks comprises LC tanksconnected in parallel.
 10. The method according to claim 8, wherein saidsecond plurality of LC tanks comprises a binary weighted array ofswitchable capacitors.
 11. The method according to claim 1, furthercomprising coupling said source of said single switching transistor to asecond switching transistor.
 12. The method according to claim 1,further comprising coupling said drain of said single switchingtransistor to a third switching transistor.
 13. A system for increasingan amplifier circuit's Q factor, the system comprising: a first LC tankthat is coupled to a source of a single switching transistor; a secondLC tank that is coupled to a drain of said single switching transistor;and an amplifier core coupled to said first LC tank and said second LCtank, wherein said amplifier core controls a gate of said singleswitching transistor to decrease a resistance of said first LC tank andsaid second LC tank by about one half, thereby increasing the Q factorby about two.
 14. The system according to claim 13, further comprising acontrol signal generator coupled to said amplifier core, wherein saidcontrol signal generator controls said gate of said single switchingtransistor.
 15. The system according to claim 13, wherein said amplifiercore tunes at least one of said first LC tank and second LC tank to afrequency of about 3.4 GHz to 4 GHz.
 16. The system according to claim13, wherein said single switching transistor comprises an NMOStransistor.
 17. The system according to claim 13, further comprising afirst plurality of LC tanks coupled to said first LC tank.
 18. Thesystem according to claim 17, wherein said first plurality of LC tankscomprises LC tanks connected in parallel.
 19. The system according toclaim 17, wherein said first plurality of LC tanks comprises a binaryweighted array of switchable capacitors.
 20. The system according toclaim 13, further comprising a second plurality of LC tanks coupled tosaid second LC tank.
 21. The system according to claim 20, wherein saidsecond plurality of LC tanks comprises LC tanks connected in parallel.22. The system according to claim 20, wherein said second plurality ofLC tanks comprises a binary weighted array of switchable capacitors. 23.The system according to claim 13, further comprising a second switchingtransistor coupled to said source of said single switching transistor.24. The system according to claim 13, further comprising a thirdswitching transistor coupled to said drain of said single switchingtransistor.
 25. A method for operating an amplifier circuit comprisingcausing, during operation of said amplifier circuit, a resistance of atleast a portion of said amplifier circuit to decrease by about one half,thereby increasing a Q factor of said amplifier circuit by about two.26. An amplifier circuit, comprising circuitry that causes, duringoperation of said amplifier circuit, a resistance of at least a portionof said amplifier circuit to decrease by about one half, therebyincreasing a Q factor of said amplifier circuit by about two.